The present invention relates to a semiconductor integrated circuit including a ring oscillator circuit constituted from an odd number of inverter stages connected to one another so that an input of the first stage is connected to an output of the final stage to form a ring.
A ring oscillator circuit having an odd number of inverter stages connected to form a ring is a well-known circuit which uses repeated charge and discharge operations. Repeated charge and discharge operations occur because the levels of input and output nodes of the inverter circuits are not stable (i.e., do not have a constant level) due to the odd number of inverter stages. A signal having a predetermined frequency is obtained through the repeated charge and discharge operations. At high oscillating frequencies, such a ring oscillator circuit undergoes a higher number of charge and discharge operations per unit time, so that the high frequency ring oscillator circuit has a large current consumption. To suppress power consumption, it is necessary that an oscillating frequency of the ring oscillator not be higher than is necessary.
In this connection, the problem of high current consumption has been highlighted due to the popularity of portable electronic devices and other apparatus operated by battery. It is desirable for batteries to last longer.
FIG. 1 shows an example of a conventional ring oscillator circuit including an element for reducing current consumption. In FIG. 1, numeral 101 denotes an oscillator circuit main portion having inverter circuits IV.sub.1 -IV.sub.5 in which the inverter stages are connected by a cascade connection and in which an input of the first stage inverter circuit IV.sub.1 is connected to an output of the fifth inverter circuit IV.sub.5 to form the ring oscillator circuit 103 having five stages. Each of the inverter circuits IV.sub.1 -IV.sub.5 is a complementary metal oxide layer semiconductor (CMOS) circuit. Numeral 1 denotes a P channel type MOS (hereafter called as PMOS) transistor within inverter circuit IV.sub.1, 2 denotes an N channel type MOS (hereafter called as NMOS) transistor within the same inverter; 3 denotes a PMOS transistor constituting the inverter circuit IV.sub.2, 4 denotes an NMOS transistor constituting the same; 5 denotes a PMOS transistor constituting the inverter circuit IV.sub.3, 6 denotes an NMOS transistor constituting the same; 7 denotes a PMOS transistor constituting the inverter circuit IV.sub.4, 8 denotes an NMOS transistor constituting the same; and 9 denotes a PMOS transistor constituting the inverter circuit IV.sub.5, and 10 denotes an NMOS transistor constituting the same.
The oscillator circuit main portion 101 includes bias circuit 104 for biasing each of the transistors 1-10 of the inverter circuits IV.sub.1 -IV.sub.5, and the bias circuit 104 comprises the PMOS transistors 11, 13, 15, 17 and 19 and the NMOS transistors 12, 14, 16, 18, and 20. The PMOS transistor 11 is connected between the PMOS transistor 1 and a power source potential V.sub.CC for biasing the transistor 1, and the NMOS transistor 12 is connected between the NMOS transistor 2 and a grounded potential for biasing the transistor 2. In the same manner, the bias transistors 13-20 are provided for biasing the inverter transistors 3-10.
Numeral 102 denotes a bias control circuit; bias control circuit 102 comprises a PMOS transistor 21, an NMOS transistor 22 and a passive resistor element 23. The source and drain of PMOS transistor 21 are connected between the power source potential V.sub.CC and a terminal on the higher potential side of the passive resistor element. The drain and gate of PMOS transistor 21 are shorted to each other and are connected to the gates of PMOS transistors 11, 13, 15, 17 and 19. The source and drain of the NMOS transistor 22 are connected between the ground potential and a terminal on the lower potential side of resistor 23. The drain and gate of NMOS transistor 22 are shorted to each other and are connected to the gates of NMOS transistors 12, 14, 16, 18 and 20.
The circuit having the above construction operates as follows. An "L" (a low level) signal is provided to an input terminal (at node nd1) of the inverter circuit IV.sub.1. Then, a node nd2 at a junction point between an output terminal of the inverter IV.sub.1 and an input terminal of the inverter IV.sub.2 rises to an "H" (a high level), and causes node nd3 at a junction point between an output terminal of the inverter IV.sub.2 and an input terminal of the inverter IV.sub.3 falls to an "L" level. In the same manner, node nd4 rises to "H", and node nd5 falls to an "L" level.
One cycle consists of the chain of operations starting with the signal on the node nd1 and ending with the signal on node nd5. In a next cycle, the node nd1 will change to a level "H", opposite to the level at node nd1 in the previous cycle. Consequently, the other nodes nd2-nd5 will invert to the opposite level as the next cycle progresses. As such cycles are repeated, it is possible for each of the nodes nd1-nd5 to generate a signal having a predetermined frequency decided by a charge and discharge time for each of the nodes nd1-nd5.
The potential at output nodes nd21 and nd22 at the gates of PMOS transistor 21 and NMOS transistor 22 is inversely proportional to a size of the resistor element 23. Accordingly, the potentials at nodes nd21 and nd22 can be reduced to near the threshold values V.sub.tp and V.sub.tn of transistors 21 and 22. In other words, the potential at nodes nd21 and nd22 is as follows: EQU V.sub.21 =V.sub.CC -V.sub.tp ( 1) EQU V.sub.22 =V.sub.tn ( 2).
The voltage V.sub.GS between the gate and source of transistors 1-10 in the oscillator circuit main portion 101 is determined by the voltages output by the bias control circuit 102. In short, V.sub.GS of the PMOS transistors 1, 3, 5, 7 or 9 is: EQU V.sub.GS =V.sub.tp ( 3);
and V.sub.GS of the NMOS transistors 2, 4, 6, 8 or 10 is: EQU V.sub.GS =V.sub.tn ( 4).
Here, the V.sub.GS provided limits the current through transistors 1-10. Since the current of the transistors 1-10 is suppressed to a minimum value when the V.sub.GS is suppressed near V.sub.tp and V.sub.tn at the respective transistors, the circuit illustrated in FIG. 1 can be used to decrease current consumption.
However, in the ring oscillation circuit 101, V.sub.Gs of the transistors 11 and 20 increases with increasing power source voltage, so that an oscillation frequency increases as shown by line F in the graph of FIG. 2A. Furthermore, there is a problem that the current consumption increases in proportion to the power source voltage.
Still furthermore, an increase in the oscillation frequency can increase the current consumption of other circuitry associated with the ring oscillator circuit. An example is when the ring oscillator circuit is used in a self-refresh circuit for a pseudo static random access memory (PSRAM). After the self-refresh circuit divides a frequency of an output of the ring oscillator circuit and transforms the frequency into a desired frequency, the self-refresh circuit performs a refresh operation at a cycle determined by the desired frequency. Even though current is ordinarily consumed during refresh operation, if the oscillation frequency of the ring oscillator is raised, the cycle for refresh operations is shortened, thereby increasing a current consumption.
Moreover, it is desired that a pause characteristic of the semiconductor memory cell requiring the refresh operation be improved in a low temperature environment. As shown by line T.sub.2 in the graph of FIG. 2B, the lower the temperature of the environment is, the smaller the refresh number needs to be. In other words, at higher environment temperatures, it is necessary to increase the refresh number per unit time by shortening the cycle of the refresh operation. The refresh cycle is generally set by matching the pause characteristic in such a manner that accurate refresh operation can be performed under the worst temperature environment (the highest temperature environment) within a temperature range for guaranteeing circuit operation. Consequently, since the number of refresh operations is much greater than necessary per unit time with decreasing temperature, this manner of setting the refresh condition results in increased current consumption.